Many electrical applications require analog-to-digital conversions that consume extremely low power. Traditionally, these analog-to-digital conversions have been performed using many different architectures and methods. All of these methods require a system clock to synchronize the execution of the analog-to-digital conversion. While the system clock aids in the system control, system clocks tend to consume relatively large amounts of power. For example, there are a number of applications, such as complementary metal-oxide semiconductor (CMOS) technologies, in which clock power is a very large contributor to the over all power consumed by the application.
The exact method used to achieve an analog-to-digital conversion vanes with each architecture. The power consumed by an analog-to-digital converter (ADC) depends on the components incorporated in each architecture. In addition to clocks, components such as comparators may consume power. When receiving an analog input signal, reference voltages or currents of comparators may be compared to a received input signal to determine which reference is closest to the input signal for conversion. Each time a comparator performs this function, power is consumed.
In order to reduce the power consumption requirements of systems that perform analog to digital conversions, many system architectures have been designed with the aim of reducing the number of comparators and/or references required. One such system architecture, the pipelined architecture, uses small flash ADCs in concert with a digital to analog converter (DAC). The output of the first flash ADC is converted back to an analog signal by a DAC and summed with the input signal. This intermediate signal is then multiplied by a scaling factor and fed into the next stage of the pipeline resulting in an analog-to-digital conversion. The pipelined architecture approach has been used successfully; however, it is disadvantageous in that the pipelined system requires the intermediate signals be generated regardless of whether the input is changing, often resulting in unnecessary power usage.
Another traditional approach, the successive approximation register (SAR), reduces the total number of power consuming components by using a single comparator to compare the input signal to multiple references, typically using a binary search pattern. This architecture reduces the power requirement of the logic in that the logic only changes state if there is a reason. However, SAR still requires a clock signal to determine when a change of states is allowed.